INVITED TALKS

Nicolas Pantano

Mirjana Stojilovic

Seonghyeon Park

Tathagata Srimani

Qiao Yu

Chung-Kuan Cheng

IMEC, Belgium

EPFL, Switzerland

POSTECH, S. Korea

Stanford Univ, US

TU Berlin, Germany

Univ of California San Diego, US

"High-speed Chip-to-Chip Links"

"Multi-Stage Routing for Next-Gen Commercial FPGAs"

"Routability Prediction and Optimization using Machine Learning"

"New Foundry Monolithic 3D BEOL Transistor+Memory Stack Unlocks Large IC Architectural Benefits Within the Same Design Footprint at the Same Technology Node"

"Understanding Memory Failure Prediction from Micro to System-Level"

"DTCO/STCO: The Scope and Challenges of the Technologies"