PROGRAM

6:00

General Chair Message — Welcome Message & Opening Remarks (15 min.)
Mustafa Badaroglu (Qualcomm, Belgium)

6:15

7:30

Session 1 — System Technology Co-Optimization for Advanced Physical Design (3 x 25 min.)
Session Chair: Yuzo Fukuzaki (TechInsights, Canada) & Ivan Ciofi (imec, Belgium)

• A novel system-level physics-based electromigration modelling framework; Application to the power delivery network
  Houman Zahedmanesh¹, Ivan Ciofi¹, Odysseas Zografos¹, Mustafa Badaroglu², and Kristof Croes^{1
  1}imec, Belgium   ²Qualcomm, Belgium
  
  
• Design and system technology co-optimization sensitivity prediction for VLSI technology development using machine learning
  Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, and Bill Lin
  University of California, San Diego, USA
  
  
• Enabling chiplet integration beyond 7nm (Invited Talk)
  Suresh Ramalingam
  Xilinx Inc., USA
  

Q&A (10 min.)

7:45

9:00

Session 2 — 3D EDA and Security (3 x 25 min.)
Session Chair: Shantanu Dutt (University of Illinois at Chicago, USA) & Seungwon Kim (University of California, San Diego, USA)

• Design and sign-off methodologies for wafer-to-wafer bonded 3D-ICs at advanced nodes (Invited)
  Giuliano Sisto¹, Rongmei Chen², Richard Chou¹, Geert Van der Plas², Eric Beyne², Rod Metcalfe¹ and Dragomir Milojevic^{2
  1}Cadence Design Systems, USA   ²imec, Belgium
  
  
• Chip stacking and packaging technology explorations for hardware security (Invited Talk)
  Makoto Nagata
  Kobe University, Japan
  
  
• Performance-aware interconnect delay insertion against EM side-channel attack
  Minmin Jiang and Vasilis Pavlidis
  University of Manchester, UK
  

Q&A (10 min.)

9:10

9:50

Keynote Address — Recent advances and future challenges in 2.5D/3D heterogeneous integration (Abstract)
                                  Tanay Karnik (Intel Corp., USA)

Q&A (10 min.)

10:00

11:15

Session 3 — Next Generation Optical Interconnects (3 x 25 min.)
Session Chair: Dirk Stroobandt (Ghent University, Belgium)

• Reconfigurable on-chip wireless interconnections through optical phased arrays
  Giovanna Calò¹, Gaetano Bellanca², Davide Bertozzi², Marina Barbiroli³, Franco Fuschini³, Giovanni Serafino⁴, Velio Tralli², and Vincenzo Petruzzelli^{1
  1}Polytechnic University of Bari, Italy   ²University of Ferrara, Italy   ³University of Bologna, Italy   ⁴TeCIP Institute, Italy
  
  
• Silicon photonics technology for terabit-scale optical I/O (Invited Talk)
  Joris Van Campenhout
  imec, Belgium
  
  
• Designing a multi-chiplet manycore system using the POPSTAR optical NoC architecture (Invited Talk)
  Yvain Thonnart
  CEA-LIST, France
  

Q&A (10 min.)

11:30

13:10

Session 4 — 3D Interconnects and Networks-on-Chips (4 x 25 min.)
Session Chair: Pascal Vivet (CEA, France) & Poona Bahrebar (Ghent University, Belgium)

• The open domain-specific architecture: An introduction (Invited Talk)
  Bapi Vinnakota
  ODSA, USA
  
  
• SID-Mesh: Diagonal mesh topology for silicon interposer in 2.5D NoC with introducing a new routing algorithm
  Babak Sharifpour, Mohammad Sharifpour, and Midia Reshadi
  Islamic Azad University, Iran
  
  
• RAMAN: Reinforcement learning inspired algorithm for mapping applications onto mesh Network-on-Chip
  Jitesh Choudhary¹, Soumya J¹, and Linga Reddy Cenkeramaddi^{2
  1}BITS Pilani, India   ²University of Agder, Norway
  
  
• Network-on-Chips for future 3D stacked dies (Invited Talk)
  Tiago Mück
  Arm, USA
  

Q&A (10 min.)

13:20

General Chair Closing Remarks — Audience Poll & Closing Remarks (5 min.)
Mustafa Badaroglu (Qualcomm, Belgium)