25th ACM/IEEE System-Level Interconnect Pathfinding
Workshop Program OPENING Ismail Bustany, AMD 07:30-08:00 Breakfast 08:20-08:30 Welcome SESSION-1: CHIP-TO-CHIP INTERFACES Ismail Bustany, AMD 08:30-09:00 Invited: High Bandwidth Density Interconnect for Chiplet
Applications Nicolas Pantano, imec, Belgium 09:00-09:30 Modularity Driven Parallel Placement Algorithm for 2.5D FPGA
Architectures Raveena Raikar, Ghent Univ, Belgium 09:30-10:00 Invited: Multi-Stage Routing for Next-Gen Commercial FPGAs Mirjana Stojilovic, EPFL, Switzerland 10:00-10:30 Coffee break SESSION-2: PHYSICAL DESIGN AND ROUTING Minsoo Kim, NVIDIA 10:30-11:00 Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization Seonghyeon Park, POSTECH, S.
Korea 11:00-11:30 On the Interconnection Complexity vs Size Trade-off in Circuit Graphs Marieke Louage, Ghent Univ., Belgium 11:30-12:00 Invited: New Foundry Monolithic 3D BEOL Transistor+Memory
Stack Unlocks Large IC Architectural Benefits Within the Same Design
Footprint at the Same Technology Node Tathagata Srimani, Stanford Univ, US 12:00-13:00 Lunch KEYNOTE Dirk Stroobandt, Ghent Univ,
Belgium 13:00-14:00 Memory-Centric Computing Onur Mutlu, ETHZ, Switzerland SESSION-3: COMPUTE-IN/NEAR MEMORY Dirk Stroobandt, Ghent Univ,
Belgium 14:00-14:30 Invited: Understanding Memory Failure Prediction from Micro to
System-Level Qiao Yu, TU Berlin, Germany 14:30-15:00 Improving Performance of Network-on-Memory Architectures via
(De-)/Compression-in-DRAM Arghavan Mohammadhassani, Drexel Univ, US 15:00-15:30 Coffee break SESSION-4: DTCO Dirk Stroobandt, Ghent Univ,
Belgium 15:30-16:00 Invited: The Scope and Challenges of Scaling in Advanced Technologies Chung-Kuan Cheng, Univ of California San Diego, US 16:00-16:30 Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration Yucheng Wang, Univ of California San Diego, US CLOSING Dirk Stroobandt, Ghent Univ,
Belgium 16:30-16:35 Closing remarks