(Pacific Time)



General Chair Message Welcome Message & Opening Remarks (15 min.)
Mustafa Badaroglu (Qualcomm, Belgium)



Session 1 System Technology Co-Optimization for Advanced Physical Design (3 x 25 min.)
Session Chair: Yuzo Fukuzaki (TechInsights, Canada) & Ivan Ciofi (imec, Belgium)

  • A novel system-level physics-based electromigration modelling framework; Application to the power delivery network
    Houman Zahedmanesh1, Ivan Ciofi1, Odysseas Zografos1, Mustafa Badaroglu2, and Kristof Croes1
    1imec, Belgium   2Qualcomm, Belgium

  • Design and system technology co-optimization sensitivity prediction for VLSI technology development using machine learning
    Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, and Bill Lin
    University of California, San Diego, USA

  • Enabling chiplet integration beyond 7nm (Invited Talk)
    Suresh Ramalingam
    Xilinx Inc., USA

Q&A (10 min.)



Session 2 3D EDA and Security (3 x 25 min.)
Session Chair: Shantanu Dutt (University of Illinois at Chicago, USA) & Seungwon Kim (University of California, San Diego, USA)

  • Design and sign-off methodologies for wafer-to-wafer bonded 3D-ICs at advanced nodes (Invited)
    Giuliano Sisto1, Rongmei Chen2, Richard Chou1, Geert Van der Plas2, Eric Beyne2, Rod Metcalfe1 and Dragomir Milojevic2
    1Cadence Design Systems, USA   2imec, Belgium

  • Chip stacking and packaging technology explorations for hardware security (Invited Talk)
    Makoto Nagata
    Kobe University, Japan

  • Performance-aware interconnect delay insertion against EM side-channel attack
    Minmin Jiang and Vasilis Pavlidis
    University of Manchester, UK

Q&A (10 min.)



Keynote Address Recent advances and future challenges in 2.5D/3D heterogeneous integration (Abstract)
                                  Tanay Karnik (Intel Corp., USA)

Session Chair: Ismail Bustany (Xilinx, USA)

Q&A (10 min.)



Session 3 Next Generation Optical Interconnects (3 x 25 min.)
Session Chair: Dirk Stroobandt (Ghent University, Belgium)

  • Reconfigurable on-chip wireless interconnections through optical phased arrays
    Giovanna Calò1, Gaetano Bellanca2, Davide Bertozzi2, Marina Barbiroli3, Franco Fuschini3, Giovanni Serafino4, Velio Tralli2, and Vincenzo Petruzzelli1
    1Polytechnic University of Bari, Italy   2University of Ferrara, Italy   3University of Bologna, Italy   4TeCIP Institute, Italy

  • Silicon photonics technology for terabit-scale optical I/O (Invited Talk)
    Joris Van Campenhout
    imec, Belgium

  • Designing a multi-chiplet manycore system using the POPSTAR optical NoC architecture (Invited Talk)
    Yvain Thonnart
    CEA-LIST, France

Q&A (10 min.)



Session 4 3D Interconnects and Networks-on-Chips (4 x 25 min.)
Session Chair: Pascal Vivet (CEA, France) & Poona Bahrebar (Ghent University, Belgium)

  • The open domain-specific architecture: An introduction (Invited Talk)
    Bapi Vinnakota

  • SID-Mesh: Diagonal mesh topology for silicon interposer in 2.5D NoC with introducing a new routing algorithm
    Babak Sharifpour, Mohammad Sharifpour, and Midia Reshadi
    Islamic Azad University, Iran

  • RAMAN: Reinforcement learning inspired algorithm for mapping applications onto mesh Network-on-Chip
    Jitesh Choudhary1, Soumya J1, and Linga Reddy Cenkeramaddi2
    1BITS Pilani, India   2University of Agder, Norway

  • Network-on-Chips for future 3D stacked dies (Invited Talk)
    Tiago Mück
    Arm, USA

Q&A (10 min.)


General Chair Closing Remarks Audience Poll & Closing Remarks (5 min.)
Mustafa Badaroglu (Qualcomm, Belgium)