| Day 1: Saturday, April 10 |
| 01:00 - 03:00 |
Session 0 |
|
Tutorial: A Priori Wire Length Estimates
Based on Rent's Rule |
|
Dirk Stroobandt (Ghent University, Belgium) |
| 03:00 - 03:30 |
Break |
| 03:30 - 04:45 |
Session 1, Opening session |
|
-(03:30 - 03:45) Welcome, Andrew B. Kahng, UCCA |
|
-(03:35 - 04:45) Invited talk: Latency and
Rent's Rule, Wilm E. Donath, IBM |
| 04:45 - 06:00 |
Session 2, Wiring estimations |
|
(04:45 - 05:10) Wire-length distribution
of three-dimensional integrated circuits, Arifur Rahman,
Andy Fan, and Rafael Reif
Massachusetts Institute of Technology, Cambridge (USA) |
|
-(05:10 - 05:35) Interconnection length
estimation during hierarchical VLSI design, Axel Hess and Gerhard
Zimmermann
University of Kaiserslautern (Germany) |
|
-(05:35 - 06:00) Wiring space estimation in
two-dimensional arrays" Jun Dong Cho
Sung Kyun Kwan University, Suwon (Korea) |
| 07:00 - 08:00 |
Workshop dinner |
| Day 2: Sunday, April 11 |
| 09:00 - 10:00 |
Session 3, Keynote speaker |
|
XXI Century Gigascale Integration (GSI)
: The Interconnect Problem, James D. Meindl
Georgia Institute of Technology, Atlanta (GA, USA) |
| 10:00 - 10:30 |
Break |
| 10:30 - 12:00 |
Session 4, Round table discussion on Rent's Rule |
|
-(10:30- - 10:40) Theory of massively
interconnected systems and Rent's rule, Pavel L. Barseghyan
DAN Technologies Inc. (Armenia) |
|
-(10:40 - 10:50) What is Rent's rule?
Wilm E. Donath
IBM T.J. Watson Research Laboratory, Yorktown Heights (NY, USA) |
|
-(10:50 - 11:00) Rent's rule: coincidence
or the result of the design process? Dirk Stroobandt
University of Ghent (Belgium) |
|
-(11:00 - 12:00) Round table discussion on the position statements |
| 12:00 - 01:00 |
Lunch |
| 01:00 - 02:40 |
Session 5, System Level Interconnect Prediction |
|
-(01:00 - 01:25) Estimating and optimizing
routing utilization in DSM design, Philip Chong and Robert K. Brayton,
University of California at Berkeley (CA, USA) |
|
-(01:25 - 01:50) Web-based tools for system-level
interconnect prediction, Thomas Grund, Phillip Christie, and Mark
D. Butala, Chemnitz University of Technology (Germany) and University of
Delaware, Newark (DE, USA) |
|
-(01:50 - 02:15) System-level performance
modeling with BACPAC - Berkeley advanced chip performance calculator,
Dennis Sylvester and Kurt Keutzer, University of California at Berkeley
(CA, USA) |
|
-(02:15 - 02:40) Floorplanner 1000 times
faster: a good predictor and constructor, A. Ranjan, K. Bazargan,
and M. Sarrafzadeh, Northwestern University, Evanston (IL, USA) |
| 02:40 - 03:10 |
Break |
| 03:10 - 05:00 |
Session 6, Round table session on system-level interconnect prediction |
|
-(03:10 - 03:20) Power and area estimation/optimization
in behavioral synthesis, Jun-Dong Cho, Sung Kyun Kwan University,
Suwon (Korea) |
|
-(03:20 - 03:30) Can fast algorithms
be used as good predictors? Majid Sarrafzadeh and Maogang Wang,
Northwestern University, Evanston (IL, USA) |
|
-(03:30 - 03:40) On wirelength estimating
for hierarchical top-down placement, Alex Zelikovsky, Georgia State
University, Atlanta (GA, USA) |
|
-(03:40 - 05:00) Round table discussion on the position statements |
| 05:00 - 05:30 |
Closing session, Dirk Stroobandt (Ghent University, Belgium) |