SLIP'07 Technical Program

Saturday, March 17, 2007  

Welcome Message 8:45-9am

A. Kennings (University of Waterloo)  

Session 1: Wire-Length and Layout Sensitivity Prediction 9-10am

Chair: Dirk Stroobandt (Ghent University)

Adaptable wire-length distribution with tunable occupation probability, S. Amakawa, T. Uezono, T. Sato, K. Okada, K. Masu ( Tokyo Institute of Technology)

Stochastic Interconnect Layout Sensitivity Model, P. Zarkesh-Ha (University of New Mexico), K. Doniger (Abbott Laboratories)  

Break 10-10:30am
Session 2: Congestion Estimation 10:30am-12:30pm

Chair: I. Mandoiu ( University of Connecticut)

Invited: Tutorial on Congestion Estimation, T. Taghavi, F. Dabiri, A. Nahapetian, M. Sarrafzadeh (University of California at Los Angeles)

An Accurate and Efficient Probabilistic Congestion Estimation Model in X Architecture, Y. Wei, S. Dong, Y. Ma, X. Hong (Tsinghua Universit)

Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction, D. Yeager, G. Lemieux (University of British Columbia)  

Lunch 12:30-2pm
Session 3: Process Variation 2-3pm

Chair: David Z. Pan ( University of Texas at Austin)

Principle Hessian Direction based Parameter Reduction for Interconnect Networks with Process Variation, A. Mitev, M. Marefat, D. Ma, J. Wang (University of Arizona)

Statistical Circuit Optimization Considering Device and Interconnect Process Variations, I-J. Lin, T.-Y. Ling, Y.-W. Chang (National Taiwan University)  

Break 3-3:30pm
Session 4: Advanced Interconnect Architectures 3:30-5:30pm

Chair: I. Markov ( University of Michigan)

Invited: Networks on Chips - keeping up with Rent's rule and Moore's law, Avinoam Kolodny (Technion-Israel Institute of Technology)

Early Wire Characterization for Predictable Network-on-Chip Global Interconnects, Ilhan Hatirnaz, Stephane Badel, N. Pazos, S. Murali, D. Atienza, Y. Leblebici, G. De Micheli (Ecole Polytechnique Federale de Lausanne)

Synthetic Traffic Generation as a Tool for Dynamic Interconnect Evaluation, W. Heirman, J. Dambre, J. Van Campenhout (Ghent University)


Sunday, March 18, 2007    

Session 5: Interconnect Technology Evaluation 9-10am

Chair: Lou Scheffer (Cadence)

Impact of Interconnect Length Changes on Effective Materials Properties (Dielectric Constant), M. Y. Lanzerotti, G. Fiorenza, R. A. Rand (IBM T.J. Watson Research Center)

Modeling of the Performance of Carbon Nanotube Bundle, Cu/Low-K and Optical On-chip Global Interconnects, H. Cho, K.-H. Koo, P. Kapur, K. Saraswat (Stanford University )  

Break 10-10:30am
Session 6: Physical Synthesis and On-Chip Delay Optimization 10:30am-12:30pm

Chair: A. Kennings (University of Waterloo)  

Invited: The Nuts and Bolts of Physical Synthesis, Charles Alpert (IBM Austin Research Laboratory)

Fast Dual-Vdd Buffering Based on Interconnect Prediction and Sampling, Y. Hu, K.H. Tam, T. Jing, L. He (University of California at Los Angeles)

Exploiting On-Chip Data Behavior for Delay Minimization, N. Satyanarayana, M. Mutyam, A. Vinaya Babu (IIIT Hyderabad)  

Lunch 12:30-2pm